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N-Channel Enhancement Mode Field Effect Transistor FEATURES
Type CEP730G CEB730G CEF730G VDSS 400V 400V 400V RDS(ON) 1 1 1 ID 5.5A 5.5A 5.5A e @VGS 10V 10V 10V
CEP730G/CEB730G CEF730G
PRELIMINARY
Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired.
D
D
G
S CEB SERIES TO-263(DD-PAK)
G
G D S
G
CEP SERIES TO-220
D
S
CEF SERIES TO-220F
S
ABSOLUTE MAXIMUM RATINGS
Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed
a
Tc = 25 C unless otherwise noted Limit Symbol TO-220/263 VDS VGS ID IDM PD TJ,Tstg
f
TO-220F
Units V V
400
30
5.5 22 83 0.66 -55 to 150 5.5 22 41 0.32
e e
A A W W/ C C
Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range
Thermal Characteristics
Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RJC RJA 1.5 62.5 Limit 2.5 65 Units C/W C/W
This is preliminary information on a new product in development now . Details are subject to change without notice . 1
Rev 1. 2009.Nov. http://www.cetsemi.com
CEP730G/CEB730G CEF730G
Electrical Characteristics
Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage
b c
Tc = 25 C unless otherwise noted Symbol BVDSS IDSS IGSSF IGSSR VGS(th) RDS(on) gFS Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd IS f VSD VGS = 0V, IS = 3A VDS = 320V, ID =3.5A, VGS = 10V Test Condition VGS = 0V, ID = 250A VDS = 400V, VGS = 0V VGS = 30V, VDS = 0V VGS = -30V, VDS = 0V VGS = VDS, ID = 250A VGS = 10V, ID = 3A VDS = 50V, ID = 5A 2 0.8 6 590 105 20 15 7 30 5 14 2.5 6 5.5 1.5 30 14 60 10 18 Min 400 10 100 -100 4 1 Typ Max Units V
A
nA nA V S pF pF pF ns ns ns ns nC nC nC A V
VDS = 25V, VGS = 0V, f = 1.0 MHz
VDD = 200V, ID = 3.5A, VGS = 10V, RGEN =12
Drain-Source Diode Characteristics and Maximun Ratings
Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature . b.Pulse Test : Pulse Width < 300s, Duty Cycle < 2% . c.Guaranteed by design, not subject to production testing. d.Limited only by maximum temperature allowed . e.Pulse width limited by safe operating area . f.Full package IS(max) = 5A .
2
CEP730G/CEB730G CEF730G
6 5 4 3 2 1 0 VGS=10,8,7,6V 12 10 8 6 4 25 C 2 0 TJ=125C -55 C 4 5 6
ID, Drain Current (A)
VGS=4V
0
1
2
3
4
5
6
ID, Drain Current (A)
1
2
3
VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics
900 750 600 450 300 150 0 Coss Crss 0 5 10 15 20 25 Ciss 2.6 2.2 1.8 1.4 1.0 0.6 0.2 -100
VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics
ID=3A VGS=10V
RDS(ON), Normalized RDS(ON), On-Resistance(Ohms)
C, Capacitance (pF)
-50
0
50
100
150
200
VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance
1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 VDS=VGS
TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature IS, Source-drain current (A)
VGS=0V
10
1
VTH, Normalized Gate-Source Threshold Voltage
ID=250A
10
0
10 -25 0 25 50 75 100 125 150
-1
0.4
0.6
0.8
1.0
1.2
1.4
TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature
VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current
3
CEP730G/CEB730G CEF730G
VGS, Gate to Source Voltage (V)
10 8 6 4 2 0 VDS=320V ID=3.5A 10
2
RDS(ON)Limit
ID, Drain Current (A)
10
1
100ms 1ms 10ms DC
10
0
0
4
8
12
16
10
-1
TC=25 C TJ=150 C Single Pulse 10
0
10
1
10
2
10
3
Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDD t on V IN VGS RGEN G RL D VOUT td(on) VOUT
10%
VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area
toff tr
90%
td(off)
90% 10%
tf
INVERTED
90%
S
VIN
50% 10%
50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
10
0
r(t),Normalized Effective Transient Thermal Impedance
D=0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2
10
-1
10
-2
Single Pulse
10
-3 -2
1. RcJC (t)=r (t) * RcJC 2. RcJC=See Datasheet 3. TJM-TC = P* RcJC (t) 4. Duty Cycle, D=t1/t2
10
10
-1
10
0
10
1
10
2
10
3
10
4
Square Wave Pulse Duration (msec) Figure 11. Normalized Thermal Transient Impedance Curve
4

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